Machine Learning for Run-Time Energy Optimisation in Many-Core Systems

In recent years, the focus of computing has moved away from performance-centric serial computation to energy-efficient parallel computation. This necessitates run-time optimisation techniques to address the dynamic resource requirements of different applications on many-core architectures. In this paper, we report on intelligent run-time algorithms which have been experimentally validated for managing energy and application performance in many-core embedded system. The algorithms are underpinned by a cross-layer system approach where the hardware, system software and application layers work together to optimise the energy-performance trade-off. Algorithm development is motivated by the biological process of how a human brain (acting as an agent) interacts with the external environment (system) changing their respective states over time. This leads to a pay-off for the action taken, and the agent eventually learns to take the optimal/best decisions in future. In particular, our online approach uses a model-free reinforcement learning algorithm that suitably selects the appropriate voltage-frequency scaling based on workload prediction to meet the applications’ performance requirements and achieve energy savings of up to 16% in comparison to state-of-the-art-techniques, when tested on four ARM A15 cores of an ODROID-XU3 platform

Dataset supporting the article entitled "Machine Learning for Run-Time Energy Optimisation in Many-Core Systems"

This dataset supports the article entitled &quot;Machine Learning for Run-Time Energy Optimisation in Many-Core Systems&quot; accepted for publication in DATE conference 2017.</span

High-speed low-complexity guided image filtering-based disparity estimation

Stereo vision is a methodology to obtain depth in a scene based on the stereo image pair. In this paper, we introduce a discrete wavelet transform (DWT)-based methodology for a state-of-the-art disparity estimation algorithm that resulted in significant performance improvement in terms of speed and computational complexity. In the initial stage of the proposed algorithm, we apply DWT to the input images, reducing the number of samples to be processed in subsequent stages by 50%, thereby decreasing computational complexity and improving processing speed. Subsequently, the architecture has been designed based on this proposed methodology and prototyped on a Xilinx Virtex-7 FPGA. The performance of the proposed methodology has been evaluated against four standard Middlebury Benchmark image pairs viz. Tsukuba, Venus, Teddy, and Cones. The proposed methodology results in the improvement of about 44.4% cycles per frame, 52% frames/s, and 61.5% and 59.6% LUT and register utilization, respectively, compared with state-of-the-art designs

High Speed Low Complexity Guided Image Filtering Based Disparity Estimation

This dataset supports the article entitled &quot;High Speed Low Complexity Guided Image Filtering Based Disparity Estimation&quot; accepted for publication in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS - I: REGULAR PAPERS JULY-2017 Data Supporting Tables and Figures: Table-1-COMPARISON OF ACCURACY USING THE MIDDLEBURY BENCHMARK Table-2-QUALITY, SPEED AND ERROR COMPARISON WITH THE RELATED WORKS Figure 9(b)-Disparity error for different wavelets Figure 9(c)-Error for Tsukuba image for different size of median filter Figure 10(b)-State-of-the-art comparison for cycles-per-frame Figure 10(c)-State-of-the-art comparison for resource utilization </span